DP8483 latch equivalent, ttl to 100k ecl level translator with latch.
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16-pin DIP or S O ECL control inputs CS provided for wire ORing of output bus 100k ECL I O compatible 3 0 ns typical propagation delay
Logic and Connection Di.
This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with CS providing for wire ORing of outputs The strobe and chip select inputs operate at ECL levels
Features
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16-pin DIP .
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